The Hynix 1Gbit GDDR3 Graphics RAM is a high-speed memory device, designed for high band width intensive application like PC graphics systems. The chip is programmable into two different configurations. In the default mode the architecture is organized as two 512Mbit memories of 8 banks, each (two CS mode). In an alternate configuration, it behaves as a conventional, 8-bank 1Gbit DRAM (one CS mode).
The Hynix H5RS1H23 uses a double data rate architecture to achieve high-speed operation. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix H5RS1H23 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix H5RS1H23 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix H5RS1H23 must be initialized.