The Hynix H5GQ1H24MFR is a high speed dynamic random access memory designed for applications requiring high band with. These devices contain the following number of bits :1Gb has 1,073,741,824 bits and sixteen-banks.
The Hynix H5GQ1H24MFR uses a 8n-prefetch architecture and DDR interface to achieve high-speed operation.
The Hynix H5GQ1H24MFR interface transfers two 32bit wide data words per WCK clock cycle to/from the I/O pins.
Corresponding to the 8n-prefetch a single write or read access consists of a 256 bit wide, two CK clock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers at the I/O pins.
The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands (address and control signals) are registered at the rising edge of CK. Address is registered at every rising edge of CK and every rising edge of CK#.
The GDDR5 SGRAM replaces the pulsed strobes (WDQS& RDQS) used in previous DRAMs such as GDDR4 with a free running differential WRITE clock (WCK/WCK#) with both input and output data registered and driven respectively at both edges of the forwarded WCK.
Read and write accesses to the GDDR5 SGRAM are burst oriented; accesses start at a selected location and continue for a total of eight locations. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command and the next rising CK# edge are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command and the next rising CK# edge are used to select the bank and the starting column location for the burst access.