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Description

The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image displayer application (Digital still camera etc.) and portable applications (portable multimedia player and portable audioplayer).
Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type ofDRAM that can run at much higher clock speeds memory.

The Hynix HY57V56820F(L)T(P) Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for theconsumer memory applications which requires large memory density and high bandwidth.
It is organized as 4banks of 8,388,608 x 8 I/O.

 

Synchronous DRAM is a type of DRAM which operates in synchronization with input clock.
The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK).
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 Input/ Output bus.
All the commands are latched in synchronization with the rising edge of CLK.

 

The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page.
An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation.

 

Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
All inputs are LVTTL compatible. Devices will have a VDD and VDDQ supply of 3.3V (nominal).

 

Features

    • Standard SDRAM Protocol
    • Internal 4bank operation
    • Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
    • All device pins are compatible with LVTTL interface
    • Low Voltage interface to reduce I/O power
    • 8,192 Refresh cycles / 64ms
    • Programmable CAS latency of 2 or 3
    • Programmable Burst Length and Burst Type
      - 1, 2, 4, 8 or full page for Sequential Burst
      - 1, 2, 4 or 8 for Interleave Burst
    • 0oC ~ 70oC Operation
    • Package Type : 54_Pin TSOPII (Lead Free, Lead)
      - HY57V56820F(L)TP Series : Lead Free
      - HY57V56820F(L)T Series : Leaded
    • This product is in compliance with the directive pertaining of RoHS.

Ordering Information

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